The present invention relates generally to networking, and more specifically to USB controllers and interface circuits.
Universal Serial Bus (USB) networks have become a very popular way for users to move data between computers and peripheral devices. Specifically, USB networks are used as personal-area wired networks that transfer data between a desktop, notebook or other computer system and devices such as printers, scanners, cameras, speakers, mice, keyboards, and hard disks. A computer may have one or more USB ports, and these may be extended further using one or more hubs. Currently, a new USB standard, USB 2 is becoming popular and replacing the USB 1 standard. USB 2 supports data transfer rates of 480 Mb/s, so called “high speed,” while USB 1 supports 12 Mb/s, “full speed” and 1.5 Mb/s, “low speed” data rates. Typically, devices such as mice and keyboards operate at a lower speed to reduce component costs, while higher bandwidth devices, such as camcorders, operate at full speed.
In each of these standards, data is organized into schedules and transmitted over a cable. Unfortunately, it takes time to arrange these schedules and retrieve the necessary data. This slows data transfers and impairing network efficiency.
Moreover, these schedules are formed of linked lists, such that it is not known what data is needed next from memory until the present data is retrieved. This causes at least two difficulties. First, the main memory must be accessed each time data is needed. This consumes system resources, making memory bandwidth unavailable for use by the rest of the computer system. Second, one way to improve efficiency is to perform these memory accesses in parallel. But since the lists are linked, the memory accesses must be done in series, and this performance advantage cannot be gained.
Thus, what is needed are circuits, methods, and apparatus that reduce the time needed to organize data packets for transmission, reduce the amount of data accessed from memory, and provide for multiple accesses of data from memory to be done in parallel.